>>Good day. This is Jim Pytel from Columbia
Gorge Community College. This is digital electronics one. This lecture’s entitled PLD
Implementation Exercise: Entering a Truth Table in
VHDL, Behavioral Approach. I can’t believe it,
but we’re going back to the Happy Cat
Cat Food Factory. We’re going to do it another
PLD elimination exercise, and this lecture kind
of serves two purposes. Number one, we’re going
to use the techniques that we just learned
in this particular unit to develop the minimum
SOP expression. Okay. And the previous time that we visited the Happy
Cat Cat Food Factory, I just gave you the expression. Now, what we’re going to do
is we’re going to pretend that we are their production
manager, and we’re going to develop the logical
expression. How did he get that
in the first place? Part two of this lecture
is, we’re actually going to show you how VHDL can
implement an expression for you. That’s kind of known as
the behavioral approach, and I can’t believe I’m showing
you guys behavioral approach before structural. We’ll go into the
differences between them, but that’s the way it happens. Behavioral approach is,
basically, you’re telling VHDL to do something and it
implements it for you in its most efficient method. There are people that
think that K-map is dead, that think SOP minimization
is dead, that think that an understanding
of Boolean laws is dead because VHDL does it for you. I’m here to tell you they are
incredibly far from the truth because you will see,
I know VHDL can do it, but look at the amount
of time it takes to do it and compare and contrast. You will end up the
same results. But if you have the skills
that I’m showing here for K-map minimization, coming up with a
minimum SOP expression, you can pretty much
reissue this thing. Okay? Whereas behavioral
approach, sometimes you’ve got to really lay it
out and write a lot. It is up to your personal
preference, however. It really will implement
the same expression. Let’s go back to the Happy Cat
Cat Food Factory, and, again, I know that you have the
minimum SOP expression from our previous examples, but what we’re going do
is we’re going to pretend that we don’t have that
and we’re going to try to develop a truth table. Basic problem statement. There are three inputs
and one output. What is the output? Well, the output is cat food. Okay? It is the constituents
of the cat food. It must have one
source of protein and at least one filler agent. Corn husks are a filler agent. Gym mats are a filler agent. Seals are a source of protein. Just on that problem statement
alone, you should be able to figure out a truth table. Okay? What are my inputs? Seals, husks, and mats. What’s my output? Cat food. I’m going to
go ahead and signify that I’ve got an acceptable
form of cat food when I get a 1. I’ll come up with all
possible combinations of input, and the next step,
think about it. Fill out the truth table. Go ahead and try it,
and pause the lecture. Go ahead and see if you can come
up and stay in this orientation. Seals, husks, mats, that way
we’re all on the same page. Go ahead and fill
out that truth table. I’m going to go ahead
and pause the lecture and see what my estimate
of it is. There you go. How did I get? Well, let’s do an
intermediary steps. Okay. Remember what I said
earlier is you could put notes off to the side. Think about it. There are no seals. There are no husks. There are no mats. There’s no inputs. There’s nothing to make it. Cats cannot live on air alone. What about the second
occurrence? 001? Okay. It’s just filler. Zero. Again, 010. It’s just corn husks,
it’s just filler. Zero. What’s the next one? Seals. No seals. Husk and mats. Two types of filler. No protein. Zero. Okay. You can make these notes, and your notes might
be different than mine. What it’s just describing
to you, 100, just protein. Zero. Aha! What’s this one? We got seals and gym mats. Don’t know if you noticed that. We even got bloodstains on that. One. Good to go. We got seals and husks, 1. Finally, the happiest cat ever. Seals, husks, and mat, one. These notes, I know it may
seem kind of dumb to you. That is going to describe to
you how that truth table works. Use those notes if it helps you. Don’t use them if they don’t. I’ve come up with
the truth table. What’s my next step? Put it in a K-map. Put it in a K-map and come up
with the minimum SOP expression. So, what’s my bear
K-map look like? Looks like this. Okay. There’s my bear K-map. How am I going to organize it? I’m going to put S and H on the
side, M on that side, because, again, I’m following the
order of the truth table, following the order
of truth table. You can do it backwards. It’s going to be hard. Okay. And, now, what I’m
going to do is go ahead and 00, 01, 11, 10, 01. Put it in the truth table. Okay. Again, I’m looking
for an SOP expression. All I need to worry
about is the 1’s. These guys right here. Put in 101. There’s a 1, 1, 1,
0; put in a 1. 1, 1, 1; put in a 1. There you go. Now, what’s the next step? Group it. Triangle
group of three or right angle group of three? No, that doesn’t exist. There’s your group of two. There’s your group of two. What’s the next step? Come up with the product
expression for the term in red. Come up for the product
expression for the term in blue. And once you’ve done
that, sum them together to get the result cat food. It’s the sum of that
product and that product. Okay. Go ahead and
see if you can come up with the product
term for the one in red, and for the one in blue. What I’m getting is
something like this. There you go. Seals and husks or
seals and mats. Last step. Does it make sense? Does seals and husks
satisfy the original problem? It needs one source of protein
and at least one filler. It certainly does. Does seals and mats? It certainly does. It makes sense. Have that sanity check. And I know we did this
really slow, but, I mean, how long did it take
me to do this? Maybe, I don’t know,
three minutes. What I’m saying is that
three minute investment to do a minimum SOP
expression and then write up in VHDL, you can do that. You have the skills to do that. And we already did that and
PLD implementation exercise. You can come up with a minimum
SOP expression and write this out really quickly in VHDL and
now compare and contrast, too. What I’m going to talk about
is the behavioral approach. Okay. The behavioral approach. I’ve already kind of
written what I want to do. I’ve got an entity. What is it? It’s called Happy Cat two. So, I’ve started the
entity Happy Cat two is, bookend it with end
Happy Cat two, semicolon. Okay. What’s in between? I’ve got my input ports. I’ve got three input ports. These guys right here. The same ones we had before
because there’s three ends. This time though,
I’ve got two outputs. What I’m going to
do is I’m going to call it a cat food
SOP out, and, then, I’m going to have another
output, cat food behavioral out. Okay. What I’m going to
try to do is show you, I’m going to come up
with two expressions. D. And they should be the same. Cat food SOP. That’s exactly what
we just came up with. Seals and husks or
seals and mats. Cat food behavioral. Once I show you some of these,
of this select statement, you will see that it will
implement the exact same output as cat food SOP. However, you’re going to have
to put a little bit more effort into it than our three
minute SOP expression. Our minimum SOP expression. I’ve got a blank
architecture statement. A big old blank architecture
statement because I want to set this thing up to do, let’s do the simplest
one thirst. I mean, let’s just come
up with the expression for cat food SOP output, and
you should know this one. This is exact same one we did in our last PLD implementation
exercise, and by the way, it’s the last one we just
came up with right here. So, just write through,
write cat food SOP output in good VHLD syntax and,
again, we’re using seals, actually spelled out;
husk, actually spelled out; mats, actually spelled out. Okay. So, go ahead and
see if you can write it, and where are we
going to write it? I would probably
write it in here. Okay? Go ahead and give it
a shot, and there you go. Cat food SOP is assigned
parenthesis seals and husks, or parenthesis — excuse me. Closed parenthesis. Or parenthesis seals and mats. Parenthesis. Semicolon. Okay. By the way, over
here is architecture, I’m calling it SOP verses
behavioral of Happy Cat two because it’s, basically what
I’m going to do is now come up with the expression for cat
food BEH, cat hood behavioral. It takes a little bit of
setting up to do this. To use what I’m going to
call the select assignment, or with select statement,
which is kind of a behavioral approach
to this. I’m going to set
things up in a vector. Notice my inputs
are standard logic. My outputs are standard logic. Okay? I kind of put
them in a vector format. Okay. I’ve already declared
them as standard logic, how do I make them a vector? What’s cool is, notice
how I put some space here. What I can do is actually
declare an internal signal. Okay? What is that
section there? That’s the declaration where
I can use an internal signal, and what I’m going do
is I’m going to make that internal signal a vector,
and, then, once I’m in my, kind of my begin portion
of my architecture, I can actually assign these
inputs to that vector. Okay? I know this may
— why am I doing this? But check it out. I’m setting up this
select statement. Okay. So, let’s go ahead and
declare an internal signal, and it’s going to be a
standard logic vector. Let’s call it SHM since
we know and we want to keep that orientation. Seals, husks, mats, and up. Oh, jeez. I can’t just write
SHM, that’s going to be bad. I’ve got to write signal. I’ve got to tell in this
declaration that it’s a signal. So, let’s call it SHM. So, signal SHM colon,
what is it? It’s going to be a
standard logic vector. And it’s kind of like that,
[inaudible] but underneath it, declare it as an input
output, remember? Because it’s something
internal to my architecture. Okay? So, I’m going to call
it standard logic vector. Okay. What’s the
size of this guy? Okay. It’s three because it’s
got seals, husks, and mats. And what I’m going to do is
I’m going to say assign an MSB and an LSB, so what’s my MSB? I can call it three down to one,
or I can do two down to zero. Either way it’s three elements, and that’s ultimately
what I want to do. I want to have three
elements, so I’m going to say two down to zero. Close it up with semicolon. Okay? So, all I’ve done right
there is declared an internal signal that I can use and how
I’m going to use it as a vector. Okay. Now, I’ve got to do
something with that signal. Maybe what I can do is
potentially assign seals to the MSB; i.e.
SHM 2, SHM 1, SHM 0. Okay? So, how do we do that within the architecture
statement? Well, it’s pretty simple. It’s kind of just
like that assignment. All I’m doing is to say,
SHM parenthesis 2, assign. What am I going to assign? Seals semicolon. SHM 1, husks. SHM 0, mats. Pretty cool, huh? And this is, again,
we’re just setting it up. We had to declare. We had to move those
things in there. We had to declare an internal
signal and move those things in there, now we could start
using our behavioral approach. This is a neat thing
that VHDL can do, and it takes a while
to implement it. What you basically do is you
tell VHDL with this vector input with that particular
combination, spit out this output. With this particular
combination, spit out the next output. You’re basically just telling
it what your truth table is. So, what you got to do is you
got a good understanding what your truth table is,
and you’re going to put in when its triple
0, spit out a 0. When it’s a 001, spit out
a 0, so on and so forth. How many times am I
going to have to do that? Eight times. This is why I’m saying,
no, the K-map is not dead. Three minutes effort, at
most, I came up with that. Two seconds of writing effort. I wrote the VHDL
expression for this. I know that I could do
the behavioral model where I’m going the
select assignment, but I’ve got to do
it eight times. Add another variable to that. Sixteen times. Add another variable to that. Thirty-two times. You get my picture? However, it’s still going to
implement the same results. And the other thing is, too, notice who I’ve assigned
first, SHM 2, that’s seals. SHM 1, that’s husks. SHM 0, that’s mats. If I said 001, what I
mean is this and not that. Critical to staying organized when you’re writing
these select statements. Okay. Let’s go ahead and
write the general formula, general format, for
the select assignments. So, the first thing is
you want to say with what? With SHM. Notice I’m not
telling it two, one, or zero. I’m saying the whole vector. Select. What am I
going to select? I’m going to select
from my truth table, but what I’m assigning
to is my output. What’s my output? Well, it’s that one. Since I’ve already done cat
food SOP, what I’m going to do is cat food BEH. And notice how I’m kind of giving myself a little
bit of indent there. I’m telling myself,
hey, I’m inside this with that particular
input select. I’m within here and
structure that I can see. Okay. I’m in that assignment, and I can potentially write
some other code below it. Okay. What do I want
as my outputs? For the first one, just
do it from top to bottom. I want to output 0. Okay? Assign a standard
logic element. Notice the single quotes
because what is my output? It’s a standard logic. It’s not a vector. So, assign it a logical 0. When, what is my input? It’s SHM, which is a vector. Double quote. Double quote. Okay. So, that’s my
input combination. What is my input combination? Reading from seals, husks, mats. Staying in MSB to LSB
order becomes critical because you cannot assign
these things backwards. Your truth table won’t work. Well, it’s triple 0. Notice the double quotation
marks for vectories [phonetic]. There you go. You got your first assignment. So, with SHM, select. Here’s my first one. Cat food is this assigned
a logic — excuse me. Standard logic, 0, when the
vector element SHM is equal to triple 0, double
quotation marks. Notice I’m commaing
[phonetic] it. What do I do for the next
element in the truth table? Well, you don’t really
have to do this again because this comma statement
means I can keep on writing. Okay? So, I’m going to sign it. What’s my next element
of my truth table? Double zero, one. Should give me an output of 0. So, output 0 when 001, comma. Keep on going. Do you see what I’m saying? You’ve got to do
this eight times. Go ahead and see if you
can write the up to seven, up to triple one, and it’s going
to look something like this. And I’m going to do something at the very end that’s
kind of cunning here. You’ll see. Okay. There you go. And I don’t know if
you guys caught this. I should have — is what is
the actual name of my output? It’s — okay. So, I’m trying to do is
compare and contrast, and I don’t know what happened
to the formatting there. Kind of compare and contrast
behavioral verses the SOP implementation. Notice I got the comma
of every single lines. If you think about this, what I’m doing is triple
0, 1, 2, 3, 4, 5, 6, 7. I’ve gotten to 7. You’d think that I’ve
closed the whole thing up because that’s all
possible combinations, right? I can’t get anything else,
and else am I missing? You should all be vectors. I’m telling it that
whole string. And, again, what’s the
MSB, the one on the left? What’s the LSB, the
one on the right? How have I just find it? MSB to LSB this way. One would think that I could
just put a semicolon right there, right? Close up the whole thing. But check this out. It’s good practice. Comma. Continue with
one more statement, and this is pretty cool. Others when others. It’s one of those cases that I
know I’ve been talking about 0’s and 1’s being the only
acceptable binary values. There are things that are
unknown, are uninitialized, or indeterminant logical levels. So, say, for example,
there is one of the sensors for these things is not
given a clear 0 or a 1. How do you want your
output to respond? Others, basically, it’s saying
that that whole grab bag. There’s a bunch. I know I’ve been just
talking about 0’s and 1’s. There are a bunch of
different types of variables that you can come across
in VHDL and we’ll talk about those a little bit
later, but for right now, there’s others out there
that I haven’t talked about. U, Z, X. You see in
a couple of those U’s in the simulation program. Okay. How do I want this
thing to respond when others? Do I want to potentially
get the FDA on me? Or I don’t know if the
FDA bothers with cat food, but when I signify that, hey,
that’s an acceptable form of sustenance for
our beloved cats. You know, maybe from the,
if it’s a known situation, maybe I want to say 0. Maybe there’s some
troubleshooting I need to do. Like I can potentially
get in a problem, if I’m saying no sensor input,
I either, no input there. I’m just saying,
yeah, that’s great, that’s great, that’s great. I don’t recommend that. Zero. So, this is a pretty
neat walkthrough right here of our first kind of
behavioral approach. What is this output right
here going to look like? Exactly like that output. What do you think
it’s going to do? It’s going to do that for
us because check it out. We came up with a minimum
expression right here. We did three minutes of
work verses nine statements. Yeah. If you don’t want to put
the effort in, if you don’t want to use minimum SOP expressions, if you totally forget
how a K-map work, yeah, you could use this behavioral. The thing is you got
to write some more. If the SOP minimum expression
came up there and not dead. VHDL has not superseded
these and understanding of the basic principles behind
digital electronics will save you a lot of effort. Okay. Last but not least,
let’s close up our architecture because that’s, again,
we’re bookending between beginning all the
way down to end, and, then, we run our simulation. The cat food SOP, cat food
behavioral through its magic, with this select statement here,
should output the same values. Okay? Just in a different
form or just in a different method
of getting there. Okay? So, that’s what
I’m talking about. The data flow verses
the behavioral. There are more than
one way to feed a cat. Okay. So, I’m currently in the
ISE project navigator WebPACK for Xilinx software,
and this is a PLD implementation environment. And, again, this VHDL program,
which I have written right here, should be portable as long as
it fits on the particular device that I’m trying to fit it on to. All I’ve done is I’ve
written the VHDL program, which we had previously
written in one note. What are the three
elements of VHDL program? Library, up here; entity,
defining the inputs and outputs of it; architecture,
defining how it behaves. What have I done initially? I’ve got a declaration,
an internal signal, which I’m calling SHM. All I’m doing is I’m making
use of internal signal, which is a standard
logic factor. Why am I doing this? I’m setting it up so I can use
this select statement later on. Begin. What I’m going to do — and this not the
best VHDL program. Why? Because I don’t
know what I’m doing. I have no comments. What I can do is
type in a comment, the double hyphen there. What I’m saying is this is the
SOP implementation that I came up with on such and such date,
and now I’m, what am I doing? Assigning standard logic inputs
into vector, so I can use it with the select statement. So, I’m basically giving
myself little bread crumbs when I come back to look
at this thing later on. Now, what am I doing? Here’s — I’m within that
select statement right here. This is the select
statement output. Compare with SOP output. Ideally, they should
be the same. Initially, notice this will
output zero if other input, you know, an uninitialize or high impedance
or an unknown state. That’s probably a pretty
good idea when you’re dealing with manufacturing of some
potentially poisonous substance. Okay? All right. So, here we go. This is our VHDL program, basically exactly what
we just vote there just in that environment. Let’s go ahead and try to do
a simulation on this thing. What am I going get? That’s the radio button. That will kill you. I’m going to go ahead
and click on it. I want to simulate
the behavioral model. Run. Save the changes, yes, because I put those
comments in there. Turn on the simulation. I’m going to go ahead and
pause, and we’re going to come back up into ISim. Okay. Here we are on ISim. Notice the difference already. Cat food SOP verses
cat food behavioral. Look at cat food behavioral. It has a zero output. Why? Because of the
other statement. Because of the other statement,
because our unknown inputs, we haven’t assigned
them anything, it’s outputting a zero. Pretty cool, huh? What is this thing right here? Okay. That’s the vector SHM. It’s an internal signal. So, that’s what’s really cool
about these simulation programs. I do get access to those things. I actually can see
those internal signals on the simulation program. If I was to hardwire this thing, I know that I’ve directly
assigned seals, husks, and mats, but let’s say those
were internal things that I couldn’t access. I do, I can visualize them. Okay? All right. So, let’s go ahead and
force a clock on this one. Seals. Force clock. What I’m going to
do is I’m going to say, leading edge, zero. One. Let’s go for
16 micro seconds. I feel like I’m doing
this thing all the time. Sixty micro seconds. Apply. What’s the next one? Husks. Okay. So far, seals was our MSB. Our next one down
should go twice as fast. Apply. That’s — again, apply. Let’s run our simulation
or 16 micro seconds. Zoom in to where I’m at. Look at seals. It’s a bunch of 0s, then a
1, 01, 01, 01, 01, 01, 01. Notice my SHM vector. This is pretty cool. Triple 0, 001, 010. It’s telling me from MSB
down to LSB what that is. Okay? It’s giving me the
state of my truth table because it’s a vector. I could also open that thing
up and it’s seeing, okay, mats is assigned to SHM 0. Husks is assigned to SHM 1. It’s pretty cool. You can see these vector values. Notice, however, there are
unknown inputs prior to our, the start of our simulation. Takes a little bit of
time to set this thing up. So, there are unknown
inputs there. So, there’s an unknown
output for our SOP expression at that initial onset
when there are unknowns. But look up at that
cat food behavioral. There is a known output
there because it’s others. That’s the power of
that other statement. What’s the gist of
this whole thing is, look beside this little
glitch at the beginning. Look at cat food SOP. Look at behavioral. They’re performing the exact
same logic function strictly by magic. It’s not magic. Our cat food SOP,
we came up with that expression using
a Karnaugh map. We came up with a minimized
expression in three minutes. We wrote the cat food
behavioral description with a select statement
in maybe eight minute with eight entrees,
but check it out. They’re still doing the
same things strictly through optimized software. It came up the exact same
expression that we came up with, which is ultimately
what we want. So, this has been a super quick
description and implementation of a PLD using all the text, all the techniques we’ve
learned thus far in unit five. And I’ve just showed
you an additional step in entering a truth
table in VHDL. Okay. This concludes this
portion of the lecture.

PLD Implementation Exercise: Entering a Truth Table in VHDL
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